Ever wondered about the real-world performance cost of defending against RowHammer in modern DDR5 DRAM?
Per-Row Activation Counting (PRAC) is the industry's latest built-in defense. While recent conferences like HPCA 2025, ISCA 2025, and the DRAMSec 2025 workshop have been buzzing with simulation-based studies on PRAC's overhead, a critical question has remained unanswered: How does it perform on actual hardware?
Our latest paper in IEEE Computer Architecture Letters, “Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads,” tackles this question head-on. By manipulating DRAM timing parameters on a real system, we made a key discovery that the average performance overhead of PRAC is a modest 1.06% on SPEC CPU 2017 (rate).
However, the story doesn't end there. We found this overhead is highly sensitive to workload characteristics, particularly DRAM access frequency and row-buffer conflict rates. This highlights the crucial role that memory controller page policies play in the ultimate performance impact of this new security feature.
We believe this is the first study to ground the PRAC performance discussion in real-world measurement. Check out our paper to learn more!
Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads
Jumin Kim, Seungmin Baek, Minbok Wi, Hwayong Nam, Michael Jaemin Kim, Sukhan Lee, Kyomin Sohn, Jung Ho Ahn
Per-Row Activation Counting (PRAC), a DRAM read disturbance mitigation method, modifies key DRAM timing parameters, reportedly causing significant performance overheads in simulator-based studies. However, given known discrepancies between simulators and real hardware, real-machine experiments are vital for accurate PRAC performance estimation. We present the first real-machine performance analysis of PRAC. After verifying timing modifications on the latest CPUs using microbenchmarks, our analysis shows that PRAC's average and maximum overheads are just 1.06% and 3.28% for the SPEC CPU2017 workloads—up to 9.15× lower than simulator-based reports. Further, we show that the close page policy minimizes this overhead by effectively hiding the elongated DRAM row precharge operations due to PRAC from the critical path.